DK-DEV-5SGXEA7N【PDF 181/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51007

2014.01.10

Figure 6-23: Deserializer Bypass

Receiver Modes in Stratix V Devices

6-25

IOE

rx_out

2

IOE supports SDR, DDR, or non-registered datapath

2

Deserializer

Bit Slip

Synchronizer

LVDS Receiver

DPA Circuitry

+

–

rx_in

10

FPGA

DOUT

DIN

DOUT

DIN

DOUT

DIN

Retimed

Data

DIN

Fabric

2

diffioclk

DPA Clock

(LOAD_EN,

rx_divfwdclk

rx_outclock

diffioclk)

Clock Mux

3

(DPA_LOAD_EN,

DPA_diffioclk, rx_divfwdclk)

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

8 Serial LVDS

Clock Phases

Fractional PLL

Note: Disabled blocks and signals are grayed out

The IOE contains two data input registers that can operate in DDR or SDR mode. In DDR mode, rx_inclock

clocks the IOE register. In SDR mode, data is directly passed through the IOE. In SDR and DDR modes, the

data width from the IOE is 1 and 2 bits, respectively.

You cannot use the DPA and data realignment circuit when you bypass the deserializer.

Receiver Modes in Stratix V Devices

The Stratix V devices support the following receiver modes:

? Non-DPA mode

? DPA mode

? Soft-CDR mode

Non-DPA Mode

The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising

edge of the serial LVDS_diffioclk clock that is produced by the left and right PLLs.

You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. The LVDS_diffioclk

clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.

The following figure shows the non-DPA datapath block diagram. In SDR and DDR modes, the data width

from the IOE is 1 and 2 bits, respectively.

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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